1. Technical Field of the Invention
The present invention relates to multiple signal match detection, and more particularly to a method and apparatus for detecting two or more signals asserted at the same time for indicating an error condition.
2. Description of the Related Art
It is desired to detect the assertion of two or more signals at the same time, such as two or more word or hit line signals of a memory system. For example, a plurality of word or hit lines are typically used to access individual memory cells, where only one hit line should be asserted at any given time to assure that the correct data is read or written. If an error condition exists where two or more hit lines are asserted, it is desired to detect and report the error condition in order to invalidate data written or otherwise retrieved.
In a circuit according to prior art, a plurality of N-channel metal-oxide semiconductor field-effect transistors (MOSFETs) have their drains connected to a common node, where the common node is pulled high through a pull-up resistor. The sources of the MOSFETs are connected to ground and their gates receive respective hit line signals. An inverter having its input connected to the common node asserts an error signal whenever the common node is pulled low. Normally, all of the hit lines are deasserted low, so that the common node is normally pulled high through the pull-up resistor. When any one hit line is asserted, the corresponding MOSFET is activated thereby providing a resistive current path to ground. This resistive current path divides the overall voltage with the pull-up resistor to reduce the voltage of the common node. However, a single N-channel MOSFET is not intended to be able to pull the voltage of the common node low enough to switch the inverter. However, if a second hit line is asserted activating another MOSFET, the combined parallel resistance of the two or more MOSFETs is supposed to pull the common node to a low enough voltage to switch the inverter, thereby asserting the error signal.
The prior art circuit described above is easily implemented, but is relatively unreliable over all voltage, temperature and process combinations. In particular, such voltage, temperature and process variations affect all components, including the pull-up resistor, the MOSFETs and the inverter, thereby changing the switch point of the circuit. The unreliability occurs because voltage, temperature, and/or process variations cause a large range for the switch point, rendering operation unpredictable over all operating conditions. In particular, such variations often cause the circuit to fail to detect multiple hit lines being asserted, or to indicate an error condition with the assertion of only one hit line.
It is desired to provide a reliable, multiple match detection circuit which is reliable over variations of voltage, temperature and process variations. Such a circuit could be used to increase the reliability of memory devices, such as a translation look-aside buffer (TLB). Such error detection would simplify the development of an operating system and memory management hardware for very efficient and fast detection of erroneous data.